Shu, Keliu.

CMOS PLL Synthesizers: Analysis and Design [electronic resource] / by Keliu Shu, Edgar Snchez-Sinencio. - XVI, 216 p. 85 illus. online resource. - The International Series in Engineering and Computer Science, Analog Circuits and Signal Processing, 783 0893-3405 ; . - The International Series in Engineering and Computer Science, Analog Circuits and Signal Processing, 783 .

Frequency Synthesizer for Wireless Applications -- PLL Frequency Synthesizer -- ?? Fractional-N PLL Synthesizer -- Enhanced Phase Switching Prescaler -- Loop Filter with Capacitance Multiplier -- Other Building Blocks of PLL -- Prototype Measurement Results -- Conclusions.

ZDB-2-ENG

CMOS PLL Synthesizers: Analysis and Design presents both fundamentals and state of the art PLL synthesizer design and analysis techniques. A complete overview of both system-level and circuit-level design and analysis are covered. A 16mW, 2.4GHz, sub-2V, S D fractional-N synthesizer prototype is implemented in 0.35mm CMOS. It features a high-speed and robust phase-switching prescaler, and a low-complexity and area-efficient loop capacitance mulitplier, which elegantly tackle speed and integration bottlenecks of PLL synthesizer. This book is useful as a PLL synthesizer manual for both academic researchers and industry design engineers.

9780387236698

10.1007/b102174 doi


Engineering.
Engineering.
Electronic and Computer Engineering.

TK1-9971

621.3